FreeBSD/src bc5f705 (r354718)sys/riscv/riscv plic.c

plic: support irq distribution

Our PLIC implementation only enables interrupts on the boot cpu.
Implement plic_bind_intr() so that they can be redistributed near the
end of boot during intr_irq_shuffle().

This also slightly modifies how enable bits are handled in an attempt to
better fit the PIC interface. plic_enable_intr()/plic_disable_intr() are
converted to manage an interrupt source's threshold value, since this
value can be used as to globally enable/disable an irq. All handing of the
per-context enable bits is moved to the new methods plic_setup_intr()
and plic_bind_intr().

Reviewed by:    br
MFC after:      3 weeks
Differential Revision:  https://reviews.freebsd.org/D21928
DeltaFile
+72-28sys/riscv/riscv/plic.c
+72-281 files

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