CommitterDimitry Andric (dim) (1)
AuthorDimitry Andric (dim) (1)
Branchesreleng/13.0 (1)


FreeBSD/src 2967f08 (r354979) — contrib/llvm/lib/Target/Mips Mips64InstrInfo.td MipsInstrFormats.td, contrib/llvm/lib/Target/Mips/AsmParser MipsAsmParser.cpp

by Dimitry Andric (dim) on ⎇
Merge commit 7bed381ea from llvm git (by Simon Atanasyan):

  [mips] Implement Octeon+ `saa` and `saad` instructions

  `saa` and `saad` are 32-bit and 64-bit store atomic add instructions.

     memory[base] = memory[base] + rt

  These instructions are available for "Octeon+" CPU. The patch adds
  support for both instructions to MIPS assembler and diassembler and
  introduces new CPU type - "octeon+".

  Next patches will implement `.set arch=octeon+` directive and
  `AFL_EXT_OCTEONP` ISA extension flag support.

  Differential Revision: https://reviews.llvm.org/D69849

This is one of the upstream changes needed for adding support for the
OCTEON+ CPU type, so that we can test Clang builds using the most
commonly available FreeBSD/mips64 reference platform, the Edge Router
Lite.

Requested by:   kevans
MFC after:      1 month
X-MFC-With:     r353358
DeltaFile
+48-3contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+18-0contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td
+13-0contrib/llvm/lib/Target/Mips/MipsInstrFormats.td
+12-0contrib/llvm/lib/Target/Mips/MipsInstrInfo.td
+10-0contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+7-2contrib/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+5-0contrib/llvm/lib/Target/Mips/Mips.td
+4-0contrib/llvm/lib/Target/Mips/MipsSubtarget.h
+2-1contrib/llvm/lib/Target/Mips/MipsScheduleP5600.td
+119-69 files

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