Displaying 1 50 of 293,544 commits (0.019s)

LLVM — cfe/trunk/lib/StaticAnalyzer/Checkers/UninitializedObject UninitializedObjectChecker.cpp

[analyzer][UninitializedObjectChecker] No longer using nonloc::LazyCompoundVal

As rightly pointed out by @NoQ, nonloc::LazyCompoundVals were only used to acquire a 
constructed object's region, which isn't what LazyCompoundVal was made for.

Differential Revision: https://reviews.llvm.org/D51300

LLVM — cfe/trunk/www/analyzer alpha_checks.html available_checks.html

[analyzer][www] Update alpha_checks.html

I added some missing doc. I have not developed any of these checkers, it might worth 
really inspecting whether I wrote something terribly incorrect.

Differential Revision: https://reviews.llvm.org/D52969

LLVM — llvm/trunk/lib/Target/X86 X86InstrSSE.td X86InstrAVX512.td, llvm/trunk/test/CodeGen/X86 widened-broadcast.ll oddshuffles.ll

[X86] Stop promoting integer loads to vXi64

Summary:
Theoretically this was done to simplify the amount of isel patterns that were needed. But 
it also meant a substantial number of our isel patterns have to match an explicit bitcast. 
By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to 
change the load type to remove the bitcast.

I had to add some additional plain load instruction patterns and a few other special 
cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like 
this promotion was hurting us more than helping.

I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems 
to relate to using getTargetConstantFromNode on a load that was shrunk due to an 
extract_subvector combine after the constant pool entry was created. So we end up decoding 
more mask elements than the load size.

I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor 
promotion.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits, RKSimon

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LLVM — llvm/trunk/lib/Target/X86 X86ShuffleDecodeConstantPool.cpp X86MCInstLower.cpp

Revert r344873 "foo"

Rebase gone wrong left this in my tree.

LLVM — llvm/trunk/lib/Target/X86 X86ISelDAGToDAG.cpp X86ISelLowering.cpp

[X86] Remove SDIVREM8_SEXT_HREG/UDIVREM8_ZEXT_HREG and their associated DAG combine and 
target bits support. Use a post isel peephole instead.

Summary:
These nodes exist to overcome an isel problem where we can generate a zero extend of an AH 
register followed by an extract subreg, and another zero extend. The first zero extend 
exists to avoid a partial register update copying the AH register into the low 8-bits. The 
second zero extend exists if the user wanted the remainder zero extended.

To make this work we had a DAG combine to morph the DIVREM opcode to a special opcode that 
included the extend. But then we had to add the new node to computeKnownBits and 
computeNumSignBits to process the extension portion.

This patch instead removes all of that and adds a late peephole to detect the two extends.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D53449

LLVM — llvm/trunk/lib/CodeGen/SelectionDAG DAGCombiner.cpp, llvm/trunk/test/CodeGen/AArch64 extract-insert.ll

[DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016)

This is a late backend subset of the IR transform added with:
D52439

We can confirm that the conversion to a 'trunc' is correct by running:
$ opt -instcombine -data-layout="e"
(assuming the IR transforms are correct; change "e" to "E" for big-endian)

As discussed in PR39016:
https://bugs.llvm.org/show_bug.cgi?id=39016
...the pattern may emerge during legalization, so that's we are waiting for an 
insertelement to become a scalar_to_vector in the pattern matching here.

The DAG allows for fun variations that are not possible in IR. Result types for 
extracts and scalar_to_vector don't necessarily match input types, so that means 
we have to be a bit more careful in the transform (see code comments).

The tests show that we don't handle cases that require a shift (as we did in the
IR version). I've left that as a potential follow-up because I'm not sure if 
that's a real concern at this late stage.

Differential Revision: https://reviews.llvm.org/D53201

LLVM — cfe/trunk/include/clang/StaticAnalyzer/Core AnalyzerOptions.h, cfe/trunk/lib/StaticAnalyzer/Core AnalyzerOptions.cpp CoreEngine.cpp

[analyzer][NFC] Fix inconsistencies in AnalyzerOptions

I'm in the process of refactoring AnalyzerOptions. The main motivation behind
here is to emit warnings if an invalid -analyzer-config option is given from the
command line, and be able to list them all.

This first NFC patch contains small modifications to make AnalyzerOptions.cpp a
little more consistent.

Differential Revision: https://reviews.llvm.org/D53274

LLVM — llvm/trunk/lib/Passes PassBuilder.cpp, llvm/trunk/lib/Transforms/IPO PassManagerBuilder.cpp

Schedule Hot Cold Splitting pass after most optimization passes

Summary:
In the new+old pass manager, hot cold splitting was schedule too early.
Thanks to Vedant for pointing this out.

Reviewers: sebpop, vsk

Reviewed By: sebpop, vsk

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D53437

LLVM — llvm/trunk/lib/Target/X86 X86ISelLowering.cpp, llvm/trunk/test/CodeGen/X86 bitcast-int-to-vector-bool-zext.ll bitcast-int-to-vector-bool-sext.ll

[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 unary shuffle 
lowering

LLVM — llvm/trunk/lib/Target/X86 X86ISelLowering.cpp X86MCInstLower.cpp

[X86] Only extract constant pool shuffle mask data with zero offsets

D53306 exposes an issue where we sometimes use constant pool data from bigger vectors than 
the target shuffle mask. This should be safe to do, but we have to be certain that we're 
using the bottom most part of the vector as the shuffle mask decoders have no way to peek 
into subvectors with non-zero offsets.

LLVM — llvm/trunk/test/MC/WebAssembly basic-assembly.s

[WebAssembly] Change tabs to spaces in basic-assembly.s

LLVM — cfe/trunk/lib/Sema SemaStmtAsm.cpp, cfe/trunk/test/Analysis cfg.cpp asm.cpp

[AST, analyzer] Transform rvalue cast outputs to lvalues (fheinous-gnu-extensions)

Despite the fact that cast expressions return rvalues, GCC still
handles such outputs as lvalues when compiling inline assembler.
In this commit, we are treating it by removing LValueToRValue
casts inside GCCAsmStmt outputs.

Differential Revision: https://reviews.llvm.org/D45416

LLVM — llvm/trunk/test/ExecutionEngine/OrcLazy global-ctors-and-dtors.ll hello.ll

[ORC] Add some more basic sanity tests for the LLJIT.

minimal.ll contains a main function that returns zero, and
single-function-call.ll contains a main function that calls a foo function that
returns zero. These minimal tests can help to rule out some trivial JIT bugs
when other tests fail.

This commit also renames hello.ll to global-ctors-and-dtors.ll, which better
reflects what it is actually testing.

LLVM — cfe/trunk/lib/Headers avx512vlbwintrin.h avx512bwintrin.h, cfe/trunk/test/CodeGen avx512vlbw-builtins.c avx512bw-builtins.c

[X86] Add more intrinsics to match icc.

This adds
_mm_loadu_epi8, _mm256_loadu_epi8, _mm512_loadu_epi8
_mm_loadu_epi16, _mm256_loadu_epi16, _mm512_loadu_epi16
_mm_storeu_epi8, _mm256_storeu_epi8, _mm512_storeu_epi8
_mm_storeu_epi16, _mm256_storeu_epi16, _mm512_storeu_epi16

LLVM — cfe/trunk/lib/Headers avx512vlintrin.h avx512fintrin.h, cfe/trunk/test/CodeGen avx512vl-builtins.c avx512f-builtins.c

[X86] Add missing intrinsics to match icc.

This adds
_mm_and_epi32, _mm_and_epi64
_mm_andnot_epi32, _mm_andnot_epi64
_mm_or_epi32, _mm_or_epi64
_mm_xor_epi32, _mm_xor_epi64
_mm256_and_epi32, _mm256_and_epi64
_mm256_andnot_epi32, _mm256_andnot_epi64
_mm256_or_epi32, _mm256_or_epi64
_mm256_xor_epi32, _mm256_xor_epi64
_mm_loadu_epi32, _mm_loadu_epi64
_mm_load_epi32, _mm_load_epi64
_mm256_loadu_epi32, _mm256_loadu_epi64
_mm256_load_epi32, _mm256_load_epi64
_mm512_loadu_epi32, _mm512_loadu_epi64
_mm512_load_epi32, _mm512_load_epi64
_mm_storeu_epi32, _mm_storeu_epi64
_mm_store_epi32, _mm_load_epi64
_mm256_storeu_epi32, _mm256_storeu_epi64
_mm256_store_epi32, _mm256_load_epi64
_mm512_storeu_epi32, _mm512_storeu_epi64
_mm512_store_epi32,V _mm512_load_epi64

LLVM — llvm/trunk/test/Transforms/InstCombine insert-extract-shuffle.ll

[InstCombine] add test for possible shuffle fold; NFC

LLVM — cfe/trunk/lib/AST VTableBuilder.cpp, cfe/trunk/lib/ASTMatchers ASTMatchersInternal.cpp

Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC

LLVM — llvm/trunk/test/Analysis/CostModel/X86 shuffle-insert_subvector.ll shuffle-extract_subvector.ll

[CostModel][X86] Add some initial extract/insert subvector shuffle cost tests

Just f64/i64 tests initially to demonstrate PR39368

LLVM — llvm/trunk/lib/Transforms/InstCombine InstCombineVectorOps.cpp

[InstCombine] use 'match' to simplify code; NFC

LLVM — llvm/trunk/lib/Transforms/InstCombine InstCombineVectorOps.cpp

[InstCombine] make code more flexible with lambda; NFC

I couldn't tell from svn history when these checks were added,
but it pre-dates the split of instcombine into its own directory
at rL92459.

The motivation for changing the check is partly shown by the
code in PR34724:
https://bugs.llvm.org/show_bug.cgi?id=34724

There are also existing regression tests for SLPVectorizer with
sequences of extract+insert that are likely assumed to become
shuffles by the vectorizer cost models.

LLVM — llvm/trunk/lib/Transforms/InstCombine InstCombineVectorOps.cpp

[InstCombine] add explanatory comment for strange vector logic; NFC

LLVM — llvm/trunk/test/Transforms/SLPVectorizer/X86 reduction_unrolled.ll

[SLPVectorizer][X86] Add mul/and/or/xor unrolled reduction tests

We miss arithmetic reduction for everything but Add/FAdd (I assume because that's the only 
cases which x86 has horizontal ops for.....)

LLVM — llvm/trunk/test/Transforms/SLPVectorizer/AArch64 transpose.ll

[SLPVectorizer] regenerate test checks; NFC

LLVM — cfe/trunk/lib/StaticAnalyzer/Core CheckerManager.cpp

[NFC][Test commit] Fix typos in a comment

LLVM — llvm/trunk/test/Analysis/CostModel/X86 reduce-smin.ll reduce-umin.ll

[CostModel][X86] Add integer vector reduction cost tests

LLVM — llvm/trunk/lib/Support Host.cpp

Replace setFeature macro with lambda to fix MSVC "shift count negative or too big" 
warnings. NFCI.
Delta File
+10 -10 llvm/trunk/lib/Support/Host.cpp
+10 -10 1 file

LLVM — lld/trunk/ELF Writer.cpp

Add an addAbsolute static function to Writer.cpp

Summary:
SymbolTable::addAbsolute() was removed in rL344305.
To me this is more readable than the lambda named `Add` and in our
out-of-tree CHERI target we use addAbsolute() in another function.

Reviewers: ruiu, espindola

Reviewed By: ruiu

Subscribers: kristina, emaste, llvm-commits

Differential Revision: https://reviews.llvm.org/D53393
Delta File
+8 -8 lld/trunk/ELF/Writer.cpp
+8 -8 1 file

LLVM — llvm/trunk/lib/CodeGen/AsmPrinter DwarfDebug.cpp, llvm/trunk/test/DebugInfo/X86 range_reloc.ll

DebugInfo: Use base address specifiers more aggressively

Using a base address specifier even for a single-element range is a size
win for object files (7 words versus 8 words - more significant savings
if the debug info is compressed (since it's 3 words of uncompressable
reloc + 4 compressable words compared to 6 uncompressable reloc + 2
compressable words) - does trade off executable size increase though.

LLVM — llvm/trunk/lib/MC MCObjectFileInfo.cpp

Add missed file from previous commit (r344838)

LLVM — llvm/trunk/lib/CodeGen/AsmPrinter DwarfUnit.cpp, llvm/trunk/lib/DebugInfo/DWARF DWARFExpression.cpp

DebugInfo: Use DW_OP_addrx in DWARFv5

Reuse addresses in the address pool, even in non-split cases.

LLVM — llvm/trunk/lib/CodeGen/AsmPrinter DwarfDebug.cpp DwarfCompileUnit.cpp, llvm/trunk/test/DebugInfo/X86 split-dwarf-v5-ranges.ll

DebugInfo: Implement debug_rnglists.dwo

Save space/relocations in .o files by keeping dwo ranges in the dwo
file rather than the .o file.

LLVM — llvm/trunk/lib/CodeGen/AsmPrinter DwarfDebug.cpp DwarfFile.h, llvm/trunk/test/DebugInfo/X86 range_reloc.ll fission-ranges.ll

DebugInfo: Use address pool forms in debug_rnglists

Save no relocations by reusing addresses from the address pool.

LLVM — llvm/trunk/include/llvm/DebugInfo/DWARF DWARFListTable.h DWARFDebugRnglists.h, llvm/trunk/lib/DebugInfo/DWARF DWARFDebugRnglists.cpp DWARFContext.cpp

llvm-dwarfdump: Support RLE_addressx and RLE_startx_length in .debug_rnglists

LLVM — llvm/trunk/include/llvm/DebugInfo/DWARF DWARFUnit.h DWARFFormValue.h, llvm/trunk/lib/CodeGen/AsmPrinter DwarfDebug.cpp DwarfUnit.cpp

DebugInfo: Use debug_addr for non-dwo addresses in DWARF 5

Putting addresses in the address pool, even with non-fission, can reduce
relocations - reusing the addresses from debug_info and debug_rnglists
(the latter coming soon)

LLVM — cfe/trunk/lib/CodeGen CGBlocks.cpp, cfe/trunk/test/CodeGenObjCXX lambda-to-block.mm

[CodeGen] Use the mangle context owned by CodeGenModule to correctly
mangle types of lambda objects captured by a block instead of creating a
new mangle context everytime a captured field type is mangled.

This fixes a bug in IRGen's block helper merging code that was
introduced in r339438 where two blocks capturing two distinct lambdas
would end up sharing helper functions and the block descriptor. This
happened because the ID number used to distinguish lambdas defined
in the same context is reset everytime a mangled context is created.

rdar://problem/45314494

LLVM — cfe/trunk/lib/CodeGen CGBuiltin.cpp CodeGenFunction.h, cfe/trunk/test/CodeGen target-builtin-noerror.c builtin-cpu-supports.c

[X86] Add support for more than 32 features for __builtin_cpu_is

libgcc supports more than 32 features by adding a new 32-bit variable __cpu_features2.

This adds the clang support for checking these feature bits.

Patches for compiler-rt and llvm to support this are coming as well.

Probably still need an additional patch for target multiversioning in clang.

Differential Revision: https://reviews.llvm.org/D53458

LLVM — llvm/trunk/include/llvm/Support X86TargetParser.def, llvm/trunk/lib/Support Host.cpp

[X86] Add additional CPUs and features to Host.cpp and X86TargetParser.def to match 
compiler-rt and enable __builtin_cpu_supports/__builtin_cpu_is support in clang

Summary: This matches LLVM to D53461 for compiler-rt.

Reviewers: echristo, erichkeane

Reviewed By: echristo

Subscribers: dberris, llvm-commits

Differential Revision: https://reviews.llvm.org/D53462

LLVM — libcxx/trunk/test/std/depr/depr.c.headers stdlib_h.pass.cpp, libcxx/trunk/test/std/language.support/support.runtime cstdlib.pass.cpp

[libcxx] [test] Don't detect Windows' UCRT with TEST_COMPILER_C1XX

The test is trying to avoid saying aligned_alloc on Windows' UCRT, which does not (and can 
not) implement aligned_alloc. However, it's testing for c1xx, meaning clang on Windows 
will fail this test when using the UCRT.

LLVM — cfe/trunk/lib/Sema SemaStmt.cpp, cfe/trunk/test/SemaCXX warn-loop-analysis.cpp

Make -Wfor-loop-analysis work with C++17

For now, disable the "variable in loop condition not modified" warning to not
be emitted when there is a structured binding variable in the loop condition.

https://bugs.llvm.org/show_bug.cgi?id=39285

LLVM — llvm/trunk/lib/Target/WebAssembly WebAssemblyInstrSIMD.td WebAssemblyISelLowering.cpp, llvm/trunk/test/CodeGen/WebAssembly simd-comparisons.ll simd-sext-inreg.ll

[WebAssembly] Implement vector sext_inreg and tests with comparisons

Summary: Depends on D53251.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53252

LLVM — llvm/trunk/lib/Target/WebAssembly WebAssemblyISelLowering.cpp WebAssemblyInstrSIMD.td, llvm/trunk/test/CodeGen/WebAssembly simd-arith.ll

[WebAssembly] Custom lower i64x2 constant shifts to avoid wrap

Summary: Depends on D53057.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53251

LLVM — cfe/trunk/lib/CodeGen CGBuiltin.cpp, cfe/trunk/test/CodeGen attr-target-mv.c builtin-cpu-supports.c

[X86] When checking the bits in cpu_features for function multiversioning dispatcher in 
the resolver, make sure all the required bits are set. Not just one of them

Summary:
The multiversioning code repurposed the code from __builtin_cpu_supports for checking if a 
single feature is enabled. That code essentially performed (_cpu_features & (1 << C)) != 
0. But with the multiversioning path, the mask is no longer guaranteed to be a power of 2. 
So we return true anytime any one of the bits in the mask is set not just all of the bits.

The correct check is (_cpu_features & mask) == mask

Reviewers: erichkeane, echristo

Reviewed By: echristo

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D53460

LLVM — cfe/trunk/include/clang/StaticAnalyzer/Core CheckerManager.h Checker.h, cfe/trunk/include/clang/StaticAnalyzer/Core/PathSensitive TaintManager.h DynamicTypeMap.h

[analyzer] Be more plugin-friendly by moving static locals into .cpp files.

The GDMIndex functions return a pointer that's used as a key for looking up
data, but addresses of local statics defined in header files aren't the same
across shared library boundaries and the result is that analyzer plugins
can't access this data.

Event types are uniqued by using the addresses of a local static defined
in a header files, but it isn't the same across shared library boundaries
and plugins can't currently handle ImplicitNullDerefEvents.

Patches by Joe Ranieri!

Differential Revision: https://reviews.llvm.org/D52905
Differential Revision: https://reviews.llvm.org/D52906

LLVM — llvm/trunk/include/llvm/CodeGen MachineRegisterInfo.h, llvm/trunk/lib/CodeGen MachineRegisterInfo.cpp MachineCSE.cpp

[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)

Change of approach, it looks like it's a much better idea to deal with
the vregs that have LLTs and reg classes both properly, than trying to
avoid creating those across all GlobalISel passes and all targets.

The change mostly touches MachineRegisterInfo::constrainRegClass,
which is apparently only used by MachineCSE. The changes are NFC for
any pipeline but one that contains MachineCSE mid-GlobalISel.

NOTE on isCallerPreservedOrConstPhysReg change in MachineCSE:

    There is no test covering it as the only way to insert a new pass
(MachineCSE) from a command line I know of is llc's -run-pass option,
which only works with MIR, but MIRParser freezes reserved registers upon
MachineFunctions creation, making it impossible to reproduce the state
that exposes the issue.

Reviwed By: aditya_nandakumar

Differential Revision: https://reviews.llvm.org/D53144

LLVM — libcxx/trunk/test/std/containers/associative/map/map.access at.pass.cpp, libcxx/trunk/test/std/containers/unord/unord.map/unord.map.elem at.pass.cpp

[libcxx] [test] Add missing <stdexcept> to map at tests.

Reviewed as https://reviews.llvm.org/D50551

LLVM — libcxx/trunk/test/std/thread/thread.threads/thread.thread.class/thread.thread.constr F.pass.cpp

Repair thread-unsafe modifications of n_alive in F.pass.cpp

In this example, the ctor of G runs in the main thread in the expression G(), and also in 
the copy ctor of G() in the DECAY_COPY inside std::thread. The main thread destroys the 
G() instance at the semicolon, and the started thread destroys the G() after it returns. 
Thus there is a race between the threads on the n_alive variable.

The fix is to join with the background thread before attempting to destroy the G in the 
main thread.

LLVM — llvm/trunk/test/tools/llvm-objdump file-headers-elf.test file-headers-pe.test, llvm/trunk/tools/llvm-objdump llvm-objdump.cpp

[llvm-objdump] Fix --file-headers (-f) option

Changed the format call to match the surrounding code. Previously it was
printing an unsigned int while the return type being printed was
long unsigned int or wider. This caused problems for big-endian systems
which were discovered on mips64.
Also, the printed address had less characters than it should because the
character count was directly obtained from the number of bytes in the
address.
The tests were adapted to fit this fix and now use longer addresses.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D53403

LLVM — llvm/trunk/lib/Analysis VectorUtils.cpp, llvm/trunk/test/Transforms/LoopVectorize intrinsic.ll

[LoopVectorize] Loop vectorization for minimum and maximum

Summary: Depends on D52766.

Reviewers: aheejin, dschuff

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52767

LLVM — llvm/trunk/lib/Target/AMDGPU SIInstructions.td, llvm/trunk/test/CodeGen/AMDGPU sub_i1.ll add_i1.ll

AMDGPU: Add support pattern for SUB of one bit

Summary:
  Add selection patterns to support one bit Sub.

Reviewers:
  rampitec, arsenm

Differential Revision:
  https://reviews.llvm.org/D52946